Jim Keller - Moore's Law in the age of AI Chips

Jim Keller giving a talk on Moore's Law at Berkeley, [LINK] And another [VIDEO] And another [LINK] DEC, PA Semi, Apple, AMD, Tesla, Intel. He's been everywhere. [LINK] The internal announcement memo: [LINK]

What makes this more bizarre than Keller’s typical short stints at previous companies is that he has done a ton of media in the last year. He’s probably given more time to journalists/interviewers in 2020 than in the previous 3 decades of his career combined. A Fortune piece from May of this year gave some insights into his plans (as well as provided a nice overview of his career) ( [LINK] ). > Keller won’t talk much about the massive chip redesign he’s overseeing—chip designers seldom do—and Intel’s new chip probably won’t be ready for another year or two. Still, both Intel and Keller have scattered some clues about how the chips might work. The new chips will cleanly separate major functions, to make it easier for the company to improve one section at a time—an approach that evokes the chiplet model Keller used at AMD. Keller also hints that Intel’s low-power Atom line of chips may figure more prominently in his future designs for PCs and servers. It doesn’t sound like at press time he was planning to leave. Keller also did a great interview on Lex Fridman’s podcast, which was released in February of this year ( [LINK] ). Keller then did a presentation at the Matroid conference (held at the end of February) ( [VIDEO] ). I hope he’s ok, since the Intel statement specifically mentioned “personal reasons”.

Jim Keller had an interesting talk recently [1] about ways of doing parallel processing to better us the billions of transistors we have - assuming the task is parallelizable. There's the scalar core (i.e the basic CPU) which is easy to program realtively. Then a scalar core with vector instructions - difficult to program efficiently. Then there are arrays of scalar cores, i.e. GPUs, so relatively easy to program again, and now a lot of startups with arrays of scalar cores each with vector engines, so expected to be most difficult to program. He didn't go into why vector instructions are hard to use efficiently, and hard for compiler writers, but I'd be interested if anyone here could explain that. 1. [VIDEO]

The pattern of holes technique in that link (MURA) is also used in UV lithography for IC fabrication (example: [VIDEO] ).